1. Field of the Invention
The present invention relates to a method of making a semiconductor device and, more particularly, to a method of making a DRAM.
2. Description of the Related Art
A conventional method of making a DRAM will be described by exemplifying a semiconductor device disclosed in Jpn. Pat. Appln. KOKAI Publication No. 3-69185 (to be referred to as a reference hereinafter). FIG. 6A is a view showing part of the drawing in this reference. FIG. 6B is a view showing the semiconductor device in FIG. 6A when viewed from the top.
FIG. 6A shows the capacitor portion of a DRAM. A silicon oxide film 101 and a silicon nitride film 102 are formed over a semiconductor substrate 100. After patterning the silicon oxide film 101 and the silicon nitride film 102, the silicon nitride film 102 is used as a mask to form a trench 103 in the semiconductor substrate 100.
A capacitive insulating film 104 is formed in the inner wall and the bottom surface of the trench 103. The trench 103 is then filled with a polysilicon film 105. A resist film 106 having an etching resistance against the polysilicon film 105 is formed over the entire surface. The resist film 106 is lithographed and developed to form an opening 107 in a portion of the periphery of the trench 103. The resist film 106 having the opening 107 is used as a mask to etch part of the polysilicon film 105, thereby forming a connect region 109 (shown in FIG. 6B).
However, the following problem is posed in the above method. That is, for example, as shown in FIG. 6B, the interval between adjacent memory cells is set to a predetermined distance w. As shown in FIG. 7, if the alignment offset of the resist pattern occurs when the resist film 106 is lithographed and developed to form the opening 107 in the portion of the periphery of the trench 103, the alignment offset of a connect region 109', the interval between the source and drain regions 108 of the adjacent memory cells is set to W' smaller than the predetermined interval w between the adjacent memory cells. For this reason, punch-through occurs between the adjacent memory cells.
Summary of the Invention
It is an object to provide a method of making a semiconductor device, in which even if the alignment offset of a resist pattern occurs when an opening is formed in a portion of the periphery of a trench, no punch-through occurs between adjacent memory cells.
According to one aspect of the present invention, there is provided a method of making a semiconductor memory device, which includes: preparing a semiconductor substrate of a first conductivity type, forming a first insulating film over the semiconductor substrate, forming a trench in the semiconductor substrate through the first insulating film, forming a second insulating film over an inner wall of the trench, filling the trench with a doped polysilicon layer, depositing a third insulating film over the first insulating film, using the third insulating film as a mask, removing the first insulating film to form an opening for defining both a transistor region and a connect region of the doped polysilicon layer at the same time, forming a transistor on the transistor region, exposing the connect region using the third insulating film as the mask, and forming a conductive layer so as to electrically connect one of source and drain regions of the transistor to the connect region.